1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and a method of designing of the semiconductor integrated circuit.
2. Related Art
A semiconductor integrated circuit device such as an LSI operates synchronously with one clock signal or a plurality of clock signals different in phase. The clock signal or clock signals supplied from outside are distributed to circuit elements, e.g., flip-flops (F/Fs), provided in the LSI and having clock terminals. By doing so, the LSI can execute such operations as data read/write operations and various arithmetic operations.
If wiring length to the flip-flop from a clock supply source differs among the respective flip-flops, a clock skew (hereinafter, sometimes simply “skew”) occurs due to difference in clock signal delay. The skew is an irregularity in time for which a clock signal reaches each circuit element from the clock supply source. The skew staggers input/output timing at which the signal is input/output to each circuit element, which possibly causes the LSI to malfunction. If frequency of the clock signal is higher, the clock skew has a larger effect on the performance of the LSI. It is, therefore, more important to suppress the clock skew as the frequency of the clock signal is higher.
To prevent occurrence of the clock skew, the conventional semiconductor integrated circuit device such as the LSI is configured to arrange H-type tree wirings or repeater circuits symmetrically. The LSI in which importance is put on symmetry of the wirings or circuits can effectively reduce skew. However, such LSI has disadvantages in that the flexibility in the arrangement of the wirings in the LSI and that in the arrangement of the respective circuit elements in the LSI is decreased and wiring cost is increased.
There is also known LSI in which buffers (final-stage buffers) are arranged on routes from meshed wirings to respective flip-flops (Patent Document 1). The Patent Document 1, however, only describes that the final-stage buffers are arranged along the meshed wirings and that as many final-stage buffers are connected to respective intersecting intervals. The Patent Document 1 is silent about a detailed method of arranging the final-stage buffers.
Accordingly, the final-stage buffers could be present in a region to which it is unnecessary to supply clocks, with the result that the conventional technique has disadvantages of high cost, increase of power consumption, narrower regions for arranging the other circuit elements, and increase of circuit area.